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型号: | 74LS153 |
厂商: |
|
描述: | dual 4-input multiplexer |
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74LS153的详细信息
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August 1986
Revised March 2000
DM74LS153
Dual 1-of-4 Line Data Selectors/Multiplexers
General Description
Features
Each of these data selectors/multiplexers contains invert-
ers and drivers to supply fully complementary, on-chip,
binary decoding data selection to the AND-OR-invert
gates. Separate strobe inputs are provided for each of the
two four-line sections.
■ Permits multiplexing from N lines to 1 line
■ Performs at parallel-to-serial conversion
■ Strobe (enable) line provided for cascading
(N lines to n lines)
■ High fan-out, low impedance, totem pole outputs
■ Typical average propagation delay times
From data
14 ns
From strobe 19 ns
From select 22 ns
■ Typical power dissipation 31 mW
Ordering Code:
Order Number Package Number
Package Description
DM74LS153M
DM74LS153N
M16A
N16E
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Function Table
Select
Inputs
Data Inputs
Strobe
Output
B
X
L
A
X
L
C0
X
L
C1
X
X
X
L
C2
X
X
X
X
X
L
C3
X
X
X
X
X
X
X
L
G
H
L
L
L
L
L
L
L
L
Y
L
L
L
L
H
X
X
X
X
X
X
H
L
L
H
H
L
L
H
X
X
X
X
H
L
H
H
H
H
L
H
X
X
H
L
H
H
H
H
Select inputs A and B are common to both sections.
H = HIGH Level
L = LOW Level
X = Don't Care
© 2000 Fairchild Semiconductor Corporation
DS006393
www.fairchildsemi.com
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