厂商ON Semiconductor 74LS164 数据手册，datasheet pdf下载

型号：	74LS164
厂商：	ON Semiconductor
描述：	low power schottky
PDF：	预览
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August 1986

Revised April 2000

DM74LS164

8-Bit Serial In/Parallel Out Shift Register

General Description

Features

■ Gated (enable/disable) serial inputs

■ Fully buffered clock and serial inputs

■ Asynchronous clear

These 8-bit shift registers feature gated serial inputs and

an asynchronous clear. A low logic level at either input

inhibits entry of the new data, and resets the first flip-flop to

the low level at the next clock pulse, thus providing com-

plete control over incoming data. A high logic level on

either input enables the other input, which will then deter-

mine the state of the first flip-flop. Data at the serial inputs

may be changed while the clock is HIGH or LOW, but only

information meeting the setup and hold time requirements

will be entered. Clocking occurs on the LOW-to-HIGH level

transition of the clock input. All inputs are diode-clamped to

minimize transmission-line effects.

■ Typical clock frequency 36 MHz

■ Typical power dissipation 80 mW

Ordering Code:

Order Number Package Number

Package Description

DM74LS164M

DM74LS164N

M14A

N14A

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

Function Table

Inputs

Outputs

Q_A

Q_B

Q_H

Clear

Clock

...

↑

Q_A0

Q_B0

Q_An

Q_H0

Q_Gn

H = HIGH Level (steady state)

L = LOW Level (steady state)

X = Don't Care (any input, including transitions)

↑ = Transition from LOW-to-HIGH level

, Q , Q = The level of Q , Q , or Q , respectively, before the

B0 H0 A B H

indicated steady-state input conditions were established.

, Q = The level of Q or Q before the most recent ↑ transition of the

clock; indicates a one-bit shift.

DS006398

www.fairchildsemi.com