Revised April 2000
8-Bit Serial In/Parallel Out Shift Register
■ Gated (enable/disable) serial inputs
■ Fully buffered clock and serial inputs
■ Asynchronous clear
These 8-bit shift registers feature gated serial inputs and
an asynchronous clear. A low logic level at either input
inhibits entry of the new data, and resets the first flip-flop to
the low level at the next clock pulse, thus providing com-
plete control over incoming data. A high logic level on
either input enables the other input, which will then deter-
mine the state of the first flip-flop. Data at the serial inputs
may be changed while the clock is HIGH or LOW, but only
information meeting the setup and hold time requirements
will be entered. Clocking occurs on the LOW-to-HIGH level
transition of the clock input. All inputs are diode-clamped to
minimize transmission-line effects.
■ Typical clock frequency 36 MHz
■ Typical power dissipation 80 mW
Order Number Package Number
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
H = HIGH Level (steady state)
L = LOW Level (steady state)
X = Don't Care (any input, including transitions)
↑ = Transition from LOW-to-HIGH level
, Q , Q = The level of Q , Q , or Q , respectively, before the
B0 H0 A B H
indicated steady-state input conditions were established.
, Q = The level of Q or Q before the most recent ↑ transition of the
clock; indicates a one-bit shift.
© 2000 Fairchild Semiconductor Corporation