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August 1986  
Revised February 1999  
Synchronous 4-Bit Up/Down Counter with Mode Control  
Two outputs have been made available to perform the cas-  
cading function: ripple clock and maximum/minimum count.  
General Description  
The DM74LS191 circuit is a synchronous, reversible, up/  
The latter output produces a high-level output pulse with a  
down counter. Synchronous operation is provided by hav-  
duration approximately equal to one complete cycle of the  
ing all flip-flops clocked simultaneously, so that the outputs  
clock when the counter overflows or underflows. The ripple  
change simultaneously when so instructed by the steering  
clock output produces a low-level output pulse equal in  
logic. This mode of operation eliminates the output count-  
width to the low-level portion of the clock input when an  
ing spikes normally associated with asynchronous (ripple  
overflow or underflow condition exists. The counters can be  
clock) counters.  
easily cascaded by feeding the ripple clock output to the  
The outputs of the four master-slave flip-flops are triggered  
on a LOW-to-HIGH level transition of the clock input, if the  
enable input is LOW. A HIGH at the enable input inhibits  
counting. Level changes at either the enable input or the  
down/up input should be made only when the clock input is  
HIGH. The direction of the count is determined by the level  
of the down/up input. When LOW, the counter counts up  
and when HIGH, it counts down.  
enable input of the succeeding counter if parallel clocking  
is used, or to the clock input if parallel enabling is used.  
The maximum/minimum count output can be used to  
accomplish look-ahead for high-speed operation.  
Counts binary  
Single down/up count control line  
Count enable control input  
The counter is fully programmable; that is, the outputs may  
be preset to either level by placing a LOW on the load input  
and entering the desired data at the data inputs. The output  
will change independent of the level of the clock input. This  
feature allows the counters to be used as modulo-N divid-  
ers by simply modifying the count length with the preset  
Ripple clock output for cascading  
Asynchronously presettable with load control  
Parallel outputs  
Cascadable for n-bit applications  
Average propagation delay 20 ns  
Typical clock frequency 25 MHz  
The clock, down/up, and load inputs are buffered to lower  
the drive requirement; which significantly reduces the num-  
ber of clock drivers, etc., required for long parallel words.  
Typical power dissipation 100 mW  
Ordering Code:  
Order Number  
Package Number  
Package Description  
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body  
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
© 1999 Fairchild Semiconductor Corporation