ON Semiconductor 
74LS74的详细信息
-
亲，您要的详细信息都在下载文档里了！
The SN74LS74A dual edge-triggered flip-flop utilizes Schottky
TTL circuitry to produce high speed D-type flip-flops. Each flip-flop
has individual clear and set inputs, and also complementary Q and Q
outputs.
Information at input D is transferred to the Q output on the
positive-going edge of the clock pulse. Clock triggering occurs at a
voltage level of the clock pulse and is not directly related to the
transition time of the positive-going pulse. When the clock input is at
either the HIGH or the LOW level, the D input signal has no effect.
LOW
POWER
SCHOTTKY
MODE SELECT – TRUTH TABLE
INPUTS
OUTPUTS
OPERATING MODE
S
D
S
D
D
Q
Q
14
Set
L
H
L
H
H
H
L
L
H
H
X
X
X
h
l
H
L
H
H
L
L
H
H
L
Reset (Clear)
*Undetermined
Load “1” (Set)
Load “0” (Reset)
1
PLASTIC
N SUFFIX
CASE 646
H
*
Both outputs will be HIGH while both S and C are LOW, but the output
D D
states are unpredictable if S and C go HIGH simultaneously. If the levels
D
D
at the set and clear are near V maximum then we cannot guarantee to meet
IL
the minimum level for V
.
OH
H, h = HIGH Voltage Level
L, I = LOW Voltage Level
X = Don’t Care
14
1
l, h (q) = Lower case letters indicate the state of the referenced input
SOIC
D SUFFIX
CASE 751A
i, h (q) = (or output) one set-up time prior to the HIGH to LOW clock transition.
ORDERING INFORMATION
GUARANTEED OPERATING RANGES
Symbol
Parameter
Supply Voltage
Min
4.75
0
Typ
5.0
25
Max
5.25
70
Unit
V
Device
Package
14 Pin DIP
14 Pin
Shipping
V
CC
SN74LS74AN
SN74LS74AD
2000 Units/Box
T
A
Operating Ambient
Temperature Range
°C
2500/Tape & Reel
I
Output Current – High
Output Current – Low
–0.4
8.0
mA
mA
OH
I
OL
Semiconductor Components Industries, LLC, 1999
1
Publication Order Number:
December, 1999 – Rev. 6
SN74LS74A/D
扫码用手机查看Datasheet
更方便
扫码关注嵌入式ARM
同类器件
新增器件
