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ADS4246IRGCT的详细信息
Manufacturer: | Texas Instruments |
---|---|
Product Category: | Analog to Digital Converters - ADC |
RoHS: | Yes |
Number of Channels: | 2 Channel |
Brand: | Texas Instruments |
Architecture: | Pipeline |
Conversion Rate: | 160 MS/s |
Resolution: | 14 bit |
Input Type: | Differential |
Interface Type: | Serial |
Operating Supply Voltage: | 1.7 V to 1.9 V |
Maximum Operating Temperature: | + 85 C |
Mounting Style: | SMD/SMT |
Package / Case: | VQFN-64 |
Development Kit: | ADS4246EVM |
Maximum Power Dissipation: | 166 mW |
Number of Converters: | 2 |
Packaging: | Reel |
Series: | ADS4246 |
SNR: | 72.8 dB |
Factory Pack Quantity: | 250 |
ADS4246IRGCT相关文档
- PCN: Conversion to smaller reel (13" to 7") and associated packing materials on Selected QFN Devices currently shipped in 13 reels
- Evaluation Kits: Low Cost Data Capture Card
- Evaluation Kits: Wideband Transmit Signal Chain Evaluation Board & Reference Design
- Evaluation Kits: ADS4246 Evaluation Module
- Evaluation Kits: TSW2200EVM: Low Cost Portable Power Supply
- Evaluation Kits: High Speed Data Capture and Pattern Generation Platform
- Function Diagram: fbd_sbas533c
- PCN: Add Cu as Alternative Wire Base Metal for Selected Device(s)
ADS4246IRGCT应用笔记
- Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio
- Driving High-Speed ADCs: Circuit Topologies and System-Level Parameter (Rev. A)
- Why Use Oversampling when Undersampling Can Do the Job? (Rev. A)
- CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters
- Shelf-Life Evaluation of Lead-Free Component Finishes
- What Designers Should Know About Data Converter Drift
- High-Speed, Analog-to-Digital Converter Basics
- CDCE62005 as Clock Solution for High-Speed ADCs
- Interleaving Analog-to-Digital Converters
- Analog-to-Digital Converter Grounding Practices Affect System Performance
- Principles of Data Acquisition and Conversion
- A Glossary of Analog-to-Digital Specifications and Performance Characteristics (Rev. B)
- Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat
- QFN Layout Guidelines
- Phase Noise Performance and Jitter Cleaning Ability of CDCE72010
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