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MC100LVEL12DG的详细信息
Manufacturer: | ON Semiconductor |
---|---|
Product Category: | Buffers & Line Drivers |
RoHS: | Yes |
Brand: | ON Semiconductor |
Number of Input Lines: | 2 |
Number of Output Lines: | 4 |
Polarity: | Non-Inverting |
Supply Voltage - Max: | 3.8 V |
Supply Voltage - Min: | 3 V |
Maximum Operating Temperature: | + 85 C |
Mounting Style: | SMD/SMT |
Package / Case: | SOIC-8 Narrow |
Packaging: | Tube |
High Level Output Current: | - 50 mA |
Logic Family: | 100LV |
Logic Type: | ECL Low Impedance Driver |
Low Level Output Current: | 50 mA |
Minimum Operating Temperature: | - 40 C |
Number of Channels per Chip: | 1 |
Output Type: | ECL |
Propagation Delay Time: | 0.58 ns |
Series: | MC100LVEL12 |
Factory Pack Quantity: | 98 |
Supply Current: | 17 mA |
MC100LVEL12DG相关文档
- Application Note: Storage and Handling of Drypack Surface Mount Device
- Application Note: Interfacing with ECLinPS™
- Application Note: Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks
- Application Note: Thermal Analysis and Reliability of WIRE BONDED ECL
- Application Note: Interfacing Between LVDS and ECL
- Application Note: ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide
- Package Drawing: SOIC-8 Narrow Body
- Application Note: Clock Management Design Using Low Skew and Low Jitter Devices
- Application Note: AC Characteristics of ECL Devices
- Application Note: Designing with PECL (ECL at +5.0 V)
- Application Note: Termination of ECL Logic Devices
- Package Drawing: DFN8 2.0x2.0x0.9mm, 0.5p
- Simulation Model: Low Voltage ECLinPS SPICE Modeling Kit
- Simulation Model: IBIS Model for MC100LVEL12DW 3.3V
- Application Note: Phase Lock Loop General Operations
- Application Note: ECL Clock Distribution Techniques
- Application Note: The ECL Translator Guide
- Package Drawing: TSSOP 8 3.0x3.0x0.95 mm
- Application Note: Clock Generation and Clock and Data Marking and Ordering Information Guide
- Application Note: Using Wire-OR Ties in ECLInPS Designs
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